CSP Die Shrink Solution for Memory Devices

The purpose of this study was to show the effectiveness of die shrink as a package solution for memory devices. In the case of the 8mm x 10mm Direct Rambus DRAM device, about 350 dies can be obtained from a single 8-inch wafer. The 85% linear shrink (15% shrink in both x and y-directions) allows an additional 150 dies from the same size wafer. This simple calculation explains the importance of die shrink. There are two basic requirements for the die shrink package solution. First, the footprint of the new package must be the same as that of the earlier package because a mounting board with multiple devices on it can not be changed to accommodate the footprint change of single device. Second, the test socket for the new package must be the same or compatible with minimal modification because the delivery time and expense for new sockets for test and burn-in are significant. In this paper, the CSP die shrink solution will be limited to a discussion of the μBGA package only. There are two different types of μBGA CSP: a package for peripheral pad die and a package for center pad die. Each type has its own package solutions for the die shrink problem. Flash, SRAM, and 64/72M Direct RDRAM are devices with peripheral bonding pads. For this study, a 6 x 8 ball matrix was used. The majority of conventional DRAMs, 128/144M and 256M Direct RDRAM are devices with a center bonding pad. A 8 x 15 ball matrix with two-row depopulation was used for the case study [1]. A total of 13 package configurations were evaluated and proposed as viable design solutions. The assembly process, package material, test, and reliability are discussed for each package configuration. Introduction The Direct RDRAM is expected to be the major DRAM device by the year 2000 [2]. To achieve its high-speed operation of as high as 1.6 gigabytes per second, the package parasitics must be well controlled [3]. The demands of portable electronics have also imposed the requirement of smaller size with high mounting density. In terms of electrical performance and package size, flip-chip or wafer level package might be the best solutions, however, these technologies have limitations in their footprint compatibility with die shrinks because no balls can be placed outside of the die perimeter. If the package uses a fine pitch ball matrix from the beginning, the problems are transferred to the mounting board design and its manufacturing cost. The chip-scale package (CSP) was identified as a reasonable trade-off between conventional packages and flip-chip type packages. μBGA package has excellent electrical performance and is an ideal size for a chip-scale package. However, the die shrink solution has caused concern among some package designers. The objective of this paper is to describe the μBGA package die shrink solution as designed especially for Direct RDRAM, Flash, and SRAM. The total cost of package assembly, test, and surface mounting is strongly affected by the ball pitch of the package. At this moment, ball pitches of 0.75mm or 0.8mm are cost effective. For this paper, 0.75mm ball pitch was assumed for all the case studies. Depending on the location of the die bonding pad, the package designs are classified into two groups: Design C# and Design P#. Here, "C" signifies center pad die and "P" signifies peripheral die pad. Direct Rambus DRAM and μBGA CSP Direct Rambus DRAMs addresses the need for additional bandwidth brought about by the rapidly increasing demands of CPUs and applications such as 3D and DVD. RDRAMs, which will replace SDRAMs in PC main memory starting in 1999, provide 1.6 gigabytes per second bandwidth (800MHz data rate) at high efficiency. To help achieve such performance levels, RDRAMs will be packaged in CSPs. Figure 1: Direct RDRAM die with edge pad (64/72M, upper) and die with center pad (128/144M, lower). CSPs offer superior electrical characteristics, as well as significant space savings, which will enable higher module 0.75 mm